1. Field of the Invention
The present invention provides an integrated circuit chip with a high area utilization rate, and more particularly, an integrated circuit chip with a process monitor circuit and probe pads of the process monitor circuit deposited in a corner cell of the integrated circuit chip.
2. Description of the Prior Art
With high developments of technology, integrated circuits (IC) have become the most important unit in electric products, such as personal computers, mobile phones, calculators, and even watches. Semiconductor technology attempts to integrate a multi-function system onto a chip, called an application specific integrated circuit, or ASIC, said system including microprocessors, analog/digital signal processors, memories, high-speed interfaces, and so on. Such complex circuits create many problems in testing and analysis.
The yield of an IC chip is affected by many factors. In order to determine whether the manufacturing process of the semiconductor affects the yield, a prior art process monitor circuit is utilized for monitoring some functions of the chip. Please refer to FIG. 1, which illustrates a schematic diagram of a prior art chip 10 capable of monitoring the functions of a chip after the manufacturing process of a semiconductor. To be concise, FIG. 1 illustrates only a corner of the chip 10. The chip 10 includes a substrate 12, a logic area 14, two input/output (or I/O) circuits 16, a corner cell 18, a plurality of probe pad areas 20, and an area for a process monitor circuit 24. For preventing damage during dicing, or skewed effect, transistors affecting the performance of the chip 10 are not allowed to be positioned in the corner cell 18. The corner cell 18 communicates with the neighboring I/O circuits 16 via a plurality of wires 19. The chip 10 receives signals from a system through a plurality of probe pads 22 in the probe pad areas 20, and transmits the signals to a plurality of logic circuits (not shown in FIG. 1) in the logic area 14 through the I/O circuits 16. After processing a series of operations, the logic circuits in the logic area 14 transmit results through the I/O circuits 16 and the probe pads 22 to the system. As shown in FIG. 1, in order to monitor whether operations of the chip 10 are incorrect owing to the manufacturing process of the semiconductor, a process monitor circuit 24 is set in the logic area 14 of the chip 10, and the process monitor circuit 24 outputs related results to a monitor system through probe pads 220 and 222 according to different user requirements. Therefore, with the results provided by the process monitor circuit 24, the monitor system can check if the yield of the chip 10 is related to the semiconductor manufacturing process. For example, the monitor system can determine whether semiconductor properties of the chip 10 conform to a specification, and whether a shift in a semiconductor property has decreased the yield.
Referring to FIG. 1, because the process monitor circuit 24 occupies a fixed area of the logic area 14, the area is reserved at design time in the logic area 14 for containing the process monitor circuit 24. Conventionally, there are two configurations for locating the process monitor circuit 24 in the logic area 14. One is to reserve an area with fixed size and form in the logic area 14 for containing the process monitor circuit 24. As a result, the design of the logic circuits in the logic area 14 needs to be based on the remaining area of the logic area 14, which increases complexity. Meanwhile, if the system requires process monitor circuits with different monitoring functions, the logic area 14 needs to reserve corresponding areas. A second configuration is to design the logic circuits of the process monitor circuit into the logic area 14 without reserving any specified area, and then to design the process monitor circuit 24 according to remaining areas of the logic circuits in the logic area 14. Obviously, an advantage of the second method is that when designing the logic circuits, the area of the process monitor circuit 24 is not a limitation. However, after the logic circuits are set in the logic area 14, the remaining area may not be large enough to contain the process monitor circuit 24, and moreover, the process monitor circuit 24 must be set taking the remaining area into consideration. Furthermore, if the system requires different process monitor circuits, the designs of the process monitor circuits can cost a significant amount of system resources. Therefore, the above-mentioned configurations of the process monitor circuit 24 must consider the logic circuits in the logic area 14, and most importantly, these configurations occupy a portion of the logic area 14, but “area” is very precious on an IC chip.
Furthermore, in FIG. 1, the probe pads 220 and 222 for the process monitor circuit 24 to transmit monitored results to the system also inevitably occupy parts of the substrate 12, so the available area for the probe pads 22 is reduced.
In summary, in order to monitor the chip 10, the prior art has to consider not only configurations and designs of the logic circuit and the process monitor circuit in the logic area, but also the space for the probe pads, which increases system resources, increases the cost of production, and wastes chip area.